System-on-Chip (SoC) integrated circuits may contain digital components, analog components, mixed digital-analog components, and radio-frequency functions together in a single chip substrate. The circuit may also be a mixed-signal system, which implements radio and baseband functions for each radio communication implementation. Such SoC circuits may be designed for mobile communication apparatuses, for example mobile user equipments such as mobile phones and touchpad apparatuses.
For such apparatuses, power consumption is a concern for preserving battery lifetime. Thus, sleep modes may be implemented where some of the functions are in idle state, so as to reduce the power consumption. However, the residual power consumption of a circuit in an idle state may be due to leakage currents which flow from the components of the circuit to the grounded portion of the circuit substrate.
Additionally, the idle state for a SoC may apply to one part of this circuit but not to another part of the same circuit. For example, an ST C040 RAM (random access memory) circuit is a two-part integrated circuit, with a first part called MATRIX and corresponding to the RAM cell array, and a second part called PERIPHERY and corresponding to the built-in logic suitable for decoding addresses of the memory cells in the array and performing read/write control towards the cells. To help reduce the leakage currents while ensuring the content stored in the memory is maintained, the ST C040 RAM is provided with a built-in switching unit capable of switching-off the periphery logic, while still supplying the memory cell array MATRIX with a retention voltage which is lower than functional power supply. Thus, the leakage current in the periphery logic is suppressed during the sleep mode of the RAM circuit.
In addition, the provision of a deep doping well in a CMOS circuit with digital functions is efficient for reducing the noise which is generated by the operation of the digital circuit. Indeed, such digital noise can interfere with radio functions if no protection is provided. However, the deep doping well is electrically coupled to upper doping wells which are arranged in the active upper layer of the circuit, and which contain components such as MOS transistors. For this reason, it is helpful for a two-part CMOS circuit, with one circuit part which is intended to be driven in the off-state while the other circuit part is maintained with a retention voltage, to have both circuit parts be provided with respective deep doping wells which are separated and electrically isolated from each other.
However, such separation of the deep doping wells may not be compatible with the circuit layout. Indeed, the separating distance between the respective active areas of the matrix and the periphery logic of a ST C040 RAM may be short, depending on the lithography technology used for producing the integrated circuit.
For the purpose of illustrating the situation before the present disclosure, FIG. 1 shows a cross-sectional diagram of a ST C040 RAM combined with deep doping well provision. The CMOS integrated circuit 100 includes a first circuit part 10 and a second circuit part 20 which are arranged close to one another in a single semiconducting substrate. For the particular case of the circuit 100 being a ST C040 RAM, the circuit part 10 may contain the memory cell array, and the circuit part 20 may contain the built-in logic which is suitable for decoding the addresses of the memory cells and performing read/write control towards the memory cells. Referring to such RAM circuit 100 for example purpose only, the circuit part 10 is denoted “MATRIX” in the Figure, and the circuit part 20 is denoted “PERIPHERY”.
The substrate of the circuit 100 comprises in each one of the circuit parts 10 and 20, a substrate surface S, an active upper layer 1, a deep doping well 2, and a bulk portion 3, in the order from the substrate surface S toward a back side of the substrate. The bulk portion 3 of the substrate extends from the first circuit part 10 to the second circuit part 20.
The deep doping well 2 is of a first doping type while the bulk portion 3 is of a second doping type. The active upper layer 1 includes at least one upper doping well of the first doping type and a remaining upper region of the second doping type in each one of the first and second circuit parts 10, 20. Each upper doping well extends down to the deep doping well 2 from the substrate surface S in the corresponding circuit part.
In addition, highly doped terminals of the second doping type are arranged in the upper doping wells of the first and second circuit parts, and other highly doped terminals of the first doping type are arranged in the remaining upper regions of the first and second circuit parts.
In FIG. 1, the following reference numbers correspond to the following elements: 11—upper doping well in the circuit part 10; 12—remaining upper region in the circuit part 10; 21—upper doping well in the circuit part 20; 22—remaining upper region in the circuit part 20; 110—highly doped terminals in the upper doping well 11; 120—highly doped terminals in the remaining upper region 12; and 210—highly doped terminals in the upper doping well 21; 220—highly doped terminals in the remaining upper region 22.
As an example, the substrate of the integrated circuit 100 may be a p-doped silicon substrate. Then, the first and second doping types are respectively n-type and p-type. Thus, each circuit region is labelled in FIG. 1 in accordance with its doping type: n for the deep doping well 2 and the upper doping wells 11 and 21, p− for the bulk portion 3 of the substrate and the remaining upper regions 12 and 22, n+ for the highly doped terminals 120 and 220 which are respectively within the upper remaining portions 12 and 22, and p+ for the highly doped terminals 110 and 210 which are respectively within the upper doping wells 11 and 21.
The upper doping wells 11 and 21, being n-doped, are provided for arranging the p-MOS transistors of the circuit 100.
For powering the circuit 100, the following supply couplings are arranged. Within both circuit parts 10 and 20, the highly doped terminals 120 and 220 are coupled to a ground supply denoted gndm, and the remaining upper regions 12 and 22 out of the highly doped terminals 120 and 220 are coupled to a substrate supply denoted gndsm. Within the first circuit part 10, the highly doped terminals 110 and the upper doping well 11 itself out of the highly doped terminals 110 are coupled to a common power supply denoted vddma, which is dedicated to the circuit part 10. In addition, within the second circuit part 20, the highly doped terminals 210 are coupled to another power supply denoted vddmp, and the upper doping well 21 itself out of the highly doped terminals 210 is coupled to a substrate power supply denoted vddsmp, with both vddmp and vddsmp supplies being dedicated to the circuit part 20.
For the ST C040 RAM example, the common power supply vddma is the power supply of the memory cell array. With the doping types indicated in FIG. 1, vddsmp is the substrate power supply for the p-MOS transistors of the periphery logic, and gndsm is the substrate supply for the n-MOS transistors of the whole RAM circuit.
Therefore, there is a need in the art for an integrated circuit designed for reduced digital noise, but including two circuit parts, one of which can be on or off while the other remains voltage-supplied.